1. Field of the Invention
The invention relates to a semiconductor device, and more particularly to a semiconductor device and a fabrication method thereof suitable for high-integration and performance devices.
2. Background of the Related Art
FIG. 1A is a cross-sectional view of a related semiconductor device and FIG. 1B is a circuit diagram of the device of FIG. 1A. As shown therein, a semiconductor substrate 1 having a p-well 1a and a n-well 1b has an active region comprising first and second transistor regions T1, T2 and a field region consisting of first and second field parts F1, F2, the first and second transistor regions T1, T2 belonging to the p-well and the n-well, respectively. Further, field oxide films 2a, 2b of a local oxidation of silicon (LOCOS) structure are respectively formed over portions of the substrate 1 having the first and second field parts F1, F2. However, in the field parts F1, F2 field oxide films (not shown) of a shallow trench isolation (STI) structure may be formed instead of the field oxide films of LOCOS.
In addition, gate electrodes 4a, 4b are formed on portions of the substrate 1 corresponding to the first and second transistor regions T1, T2, respectively, and gate oxide films 3a, 3b are respectively formed therebetween. Impurity regions 5a, 5b doped with first and second conductive impurities are formed in the first and second transistor regions T1, T2, respectively, at both sides of each of the gate electrodes 4a, 4b.Here, the impurity regions 5a, 5b serve as source and drain, and the first conductive impurity is a n-type while the second conductive impurity is a p-type.
Further, a layer of insulating film 6 having a plurality of contact holes 6a is formed over a surface of the structure. The contact holes 6a expose portions of the substrate 1 corresponding to the impurity regions 5a, 5b. First, second and third wiring patterns 7a, 7b, 7c are formed in the contact holes 6a and on an upper surface of the layer-insulating film 6. As shown in FIGS. 1A and 1B, the first, second and third wiring patterns 7a, 7b, 7c are used as a ground (GND) line, an output voltage (VOUT) line, and a source voltage (VDD) line, respectively, and the gate electrodes 4a, 4b are respectively used as an input voltage (Vin) line.
A protection film pattern 8 having a plurality of openings (or bonding pad units) 8a is formed to prevent scratching and contamination of the structure surface. The openings 8a expose portions of the wiring patterns 7a, 7b, 7c. The portions of the wiring patterns 7a, 7b, 7c exposed by the openings 8a are referred to as bonding pads 9a, 9b, 9c, 9d. The bonding pad 9a which corresponds to the second wiring pattern 7a is connected to ground.
In such related semiconductor devices, as the sizes of devices integrated on the substrate decreases due to high integration of devices, the number of bonding pads which are connected to electrodes of the devices also increases, which results in an increase in the size of the bonding pads. Further, since voltage drop occurs to wiring lines which are electrically connected to the bonding pads connected to the source and ground, operational properties of the devices deteriorate.
The above description and/or references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
Accordingly, the invention is directed to a semiconductor device and a fabrication method thereof which obviates at least the above-described problems and disadvantages.
An object of the invention is to stabilize operational properties of the integrated devices.
Another objection of the invention is to prevent voltage drop in a ground line.
Another object of the invention is to form a metal layer which is linked with a wiring layer serving as a ground line formed at a bottom surface of the substrate.
To achieve these and other advantages of the invention, as embodied and broadly described, a semiconductor package according to a preferred embodiment of the invention is provided that includes: a semiconductor substrate having an active region comprising two transistor regions, a ground region and two field regions; field oxide films formed on the substrate in the field regions, respectively; gate electrodes formed over predetermined portions of the substrate corresponding to the transistor regions, respectively; gate oxide films interposed between the substrate and the corresponding gate electrodes; impurity regions doped with first and second conductive impurities, respectively, which are formed on both sides of each of the gate electrodes in the transistor regions, respectively; a layer-insulating film having a plurality of contact holes formed over the semiconductor substrate, the field oxide films, the gate electrodes and the impurity regions, the layer-insulating film exposing portions of an upper surface of the substrate corresponding to the ground region and the impurity regions; first, second and third wiring layer patterns formed on the layer-insulating film and in the contact holes; a protection film pattern having a plurality of contact holes formed over the semiconductor substrate, the field oxide films, the gate electrodes, the impurity regions, the layer-insulating film and the first, second and third wiring layer patterns, the protection film pattern forming bonding pads corresponding to the first, second and third wiring layer patterns, respectively; a hole formed on a portion of a bottom surface of the substrate corresponding to the ground region; and a metal layer formed on a bottom surface of the substrate and on an inner surface of the hole.
Also, to achieve the above object of the invention, there is provided according to a preferred embodiment of the invention a fabrication method of a semiconductor device, including: providing a semiconductor substrate having an active region comprising first and second transistor regions, a ground region and first and second field regions; forming field oxide films on the substrate in the field regions, respectively; forming gate electrodes over predetermined portions of the substrate corresponding to the first and second transistor regions, respectively; interposing gate oxide films between the substrate and the corresponding gate electrodes; forming, in a separate process, impurity regions doped with first and second conductive impurities, respectively, which are formed on both sides of each of the gate electrodes in the transistor regions, respectively; forming a first conductive ion diffusion layer in the ground region; forming a layer-insulating film having a plurality of contact holes over the semiconductor substrate, the field oxide films, the gate electrodes, the conductive ion diffusion layer and the impurity regions, the layer-insulating film exposing portions of an upper surface of the substrate corresponding to the impurity regions and the ion diffusion layer; forming first, second and third wiring layer patterns on the layer-insulating film and in the contact holes by deposing a wiring layer and then selectively etching the layer to form the patterns; forming a protection film pattern having a plurality of contact holes (or bonding pad units) by depositing a protection film over the semiconductor substrate, the field oxide films, the gate electrodes, the impurity regions, the conductive ion diffusion layer, the layer-insulating film and the first, second and third wiring layer patterns and selectively etching the protection film for thereby forming bonding pads; forming a hole in a bottom surface of the substrate corresponding to the ground region; and forming a metal layer on a bottom surface of the substrate and on an inner surface of the hole.
The active region comprising the transistor regions, the ground region and the field regions are preferably formed by forming a pad oxide film on the substrate by thermal oxidation; forming a mask layer by depositing nitrides silicon over the pad oxide film by chemical vapor deposition; and patterning the mask layer and the pad oxide film by photo-etching to thereby expose portions of the substrate; however, other methods may also be appropriate.
Each field oxide film preferably has a local oxidation of silicon structure or a shallow trench isolation structure. The gate electrode are preferably formed by depositing at least one of amorphous silicon or polycrystalline silicon which is doped with an impurity over the field regions and the gate oxide films formed on transistor regions by chemical vapor deposition; and patterning the silicon by photo-etching so that the silicon remains at predetermined portions of the first and second transistor regions; however, other methods may also be appropriate.
The impurity regions and the ion diffusion layer are preferably formed by forming a first photoresist pattern on portions of the substrate corresponding to the ground region and the second transistor region; ion-implanting the first conductive impurity into the first transistor region by masking the first photoresist pattern; removing the first photoresist pattern; forming a second photoresist pattern on a portion of the substrate of the first transistor region; and ion-implanting the second conductive impurity into the ground region and the second transistor region; however, other methods may also be appropriate. The first and second conductive impurities preferably have opposite types.
The first, second and third wiring layer patterns are preferably connected to an output voltage line, a ground line and a source voltage line, respectively. Furthermore, the second wiring layer pattern may be connected to at least one of the impurity regions. Further, the second wiring layer pattern is preferably connected to the ion diffusion layer of the ground region. Each of the first, second and third wiring layer patterns and the metal layer are preferably formed of at least one of aluminum, aluminum-alloy and copper.
The hole is preferably formed by making a portion of the bottom surface of the substrate corresponding to the ground region porous silicon by the electropolishing system; and selectively etching the porous silicon portion. The metal layer may be linked with the second wiring layer pattern, thereby serving as the ground line.
The protection film pattern is preferably formed of at least one of phosphorous silicate glass, silicon oxide or silicon nitrides, or the combination thereof The bonding pad corresponding to the second wiring layer pattern is preferably connected to the ground.
The invention can be achieved in a whole or in parts by a semiconductor device, comprising: a substrate; a first transistor formed in a first region of the substrate, the transistor having a first doped region formed in the first region, a second doped region formed in the first region and a control electrode formed between the first and second doped regions; a second transistor formed in a second region of the substrate, the second transistor having a third doped region formed in the second region, a fourth doped region formed in the second region and a control electrode formed between the third and fourth doped regions, wherein the first doped region is coupled for providing an output voltage, the fourth doped region is coupled for receiving a source voltage and the second and third electrode are connected to each other for receiving a ground voltage.
The invention can also be achieved in whole or in parts by an integrated device comprising: a substrate having first and second surfaces, which are opposing surfaces; a first semiconductor device formed in a first region of the substrate; a second semiconductor device formed in a second region of the substrate; a contact hole formed through the second surface of the substrate and separating the first and second regions; and a conductive layer formed in the contact hole, wherein the first and second semiconductor devices and the conductive layer are coupled to each other by a wiring layer formed over the first surface of the substrate, the wiring layer having first, second and third protrusions, the first, second and third protrusions being in contact with the first and second semiconductor devices and the conductive layer, respectively.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.